1. Field of the Invention
The present invention relates to a semiconductor memory circuit, more particularly to a semiconductor static memory circuit.
2. Description of the Prior Art
Generally, a semiconductor memory circuit of the static type comprises, as basic constituent elements, a plurality of pairs of bit lines (BL, BL) extending in Y direction, a plurality of memory cells located inside each pair of bit lines and connected thereto, a pair of load transistors inserted in each pair of bit lines, word lines extending in the X direction for selecting one of the memory cells to be accessed, and so on. The above-mentioned conventional semiconductor memory circuit, however, suffers from two shortcomings, i.e., an unnecessarily large power consumption and a long access time.
The unnecessarily large power consumption is due to the fact that there is always a continuous current flowing in one of the bit lines via the corresponding load transistor.
The long access time is due to the fact that in transferring data from an accessed memory cell to the corresponding bit line, the memory cell must absorb the continuous current via its transistors and transfer the stored data to the corresponding bit line. This naturally slows down the reading speed for the data. Related to this is the mutual conductance g.sub.m, mainly the g.sub.m of the load transistor. Access time can be improved by increasing the g.sub.m. However, the larger the g.sub.m, the larger the size of the transistor itself. The desire for high integration density has therefore led, in most cases, to the g.sub.m being designed smaller and smaller, at the expense of the access time.